1. Field of the Invention
The present invention generally relates to a process to form planarized shallow trench isolation structures using a non-conformal high density plasma (HDP) oxide deposition.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by dielectric layers.
As integrated circuit device technology has advanced and integrated circuit device dimensions have decreased, it has become increasingly common within advanced integrated circuits to employ trench isolation methods such as shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods to form trench isolation regions nominally co-planar with adjoining active semiconductor regions of semiconductor substrates. Such trench isolation methods typically employ a chemical mechanical polish (CMP) planarizing method to provide a nominally planarized surface to a trench isolation region foxned from a trench fill dielectric layer formed within the trench. Trench isolation regions nominally co-planar with active semiconductor regions within semiconductor substrates are desirable since they optimize, when subsequently forming patterned layers upon those nominally co-planar trench isolation regions and active semiconductor regions the limited depth of focus typically achievable with advanced photo exposure.
Two major challenges in achieving the shallow trench isolation (STI) structure are: (1) filling the narrow trenches without voids or seams defect, and (2) planarization of trenches of diverse widths. Conventional STI processes may employ conformal low pressure chemical vapor deposition (LPCVD) TEOS deposition and a complicated planarization process which uses two step photo-resist coating, reactive ion etch (RIE) etch back and chemical mechanical polish (CMP). Due to the nature of conformal LPCVD TEOS deposition, seams are generally present in the LPCVD TEOS filled shallow trench isolation region. The seams become a major problem as the device dimensions scale downward and the aspect ratio of the STI increases.